Computer Science

Computer Science ›› 2022, Vol. 49 ›› Issue (6): 73-80.doi: 10.11896/jsjkx.210900045

• High Performance Computing • Previous Articles     Next Articles

Study on Preprocessing Algorithm for Partition Reconnection of Unstructured-grid Based on Domestic Many-core Architecture

YE Yue-jin1, LI Fang1, CHEN De-xun2, GUO Heng2, CHEN Xin1   

  1. 1 National Supercomputing Center in Wuxi,Wuxi,Jiangsu 214000,China
    2 Department of Computer Science and Technology,Tsinghua University,Beijin 100084,China
  • Received:2021-09-05 Revised:2022-02-21 Online:2022-06-15 Published:2022-06-08
  • About author:YE Yue-jin,born in 1991,master,engineer,is a member of China Computer Federation.His main research interests include high performance computing and so on.
    LI Fang,born in 1980,postgraduate,Ph.D,associate professor.Her main research interests include high perfor-mance computing and so on.
  • Supported by:
    National High Performance Computing Foundation of China(2020YFB0204804,2016YFB0201100).

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Abstract: How to efficiently solve the discrete-memory-accessing problem of unstructed-grid is one of the hot-spot issues in the field of parallel algorithms and application in scientific and engineering computing.The distributed block reconnection optimization algorithm,which is designed on the basis of domestic Sunway heterogeneous many-core architecture,can maintain high computing performance when solving the problem of unstructured sparsity in applications.After deeply analyzing the on-chip communication mechanism of the many-core architecture,an efficient message grouping strategy is designed to improve the bandwidth utilization of on-chip array on the slave core.At the same time,a barrier-free data distribution algorithm is combined to give full play to the network perfor-mance of the domestic heterogeneous many-core architecture.Through the establishment of perfor-mance models and experimental analysis,the average memory bandwidth of the proposed algorithm can reach more than 70% of the theoretical value under different memory access situations.Compared with the serial algorithm on the master core,it has an ave-rage of 10 times and a maximum of 45 times performance acceleration.At the same time,the universal applicability of the algorithm is proved by application tests in different fields.

Key words: Barrier-free data distribution, Domestic many-core architecture, Message grouping, On-chip communication, Unstructed-grid

CLC Number: 

  • TP311
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