Abstract: The high performance embedded computing systems need considerable computational power and flexibility to meet various application rectuirements. A reconfigurable SoPC design based on Xilinx FPGA was presented. The system uses a dedicated hardware accelerator to process computational intensive tasks, and the accelerator can be dynamically configured during run-time. The hardware processing engine can be coupled to the host system as a CPU coprocessor,a PLB accelerator or an MPMC accelerator. Based on the experimental result that the MPMC accelerator had the highest performance, a reconfigurable MPMC accelerator was designed and integrated into the SoPC system. I}he experiments used 128-bit AES encryption and decryption as case studies. Features such as hardware resource utilization and reconfi guration latency for the reconfigurable system were also studied.

Key words: Embedded computing, System on programmable chip, Rcconfigurable computing, Co-proccssing, Accelerator