Abstract: In order to reduce power consumption of SRAM, an optimized SRAM was presented. I}echnology with isolalion of operation data was introduced into fast inputs,division of bus data was made to multiple bits of comparator; gating clock was added into big clock network, many modes of power control and isolation logic were increased;SRAM64K X 32 was separated into 8 sub blocks of SRAMBK X 32，which were connected with signals to select chip through logic of one selected from eight so that only one of sub blocks can be in read-write operation. The optimized SRAM64KX32 was used in SOC and power consumption of each part was mcasurai by adding bypass logic. `hhe SOC design was successfully implemented in 90nm CMOS process. The testing results indicate that power saving of the optimined SRAM64KX 32 is 29. 569%and area only increased by 0. 836%.

Key words: Low power, Isolation of operation data, Division of bus data, Mode of power control, Bypass logic