Abstract: With the rapid advancement of artificial intelligence,RISC-V instruction set extended neural network accelerators have become a research hotspot.Deep learning compilers are critical for efficiently deploying neural network models on hardware platforms.However,modifying the tuning rules of existing compilers based on hardware characteristics places extremely high demands on developers.At the same time,existing compilers lack compilation support for specialized transposition hardware units and cannot achieve efficient transposition through data flow reconstruction,resulting in the performance potential of such hardware not being fully utilized.To address these issues,this paper first designs an MLIR-based compiler toolchain targeting RISC-V neural network accelerators,enabling end-to-end model deployment.Secondly,it introduces hardware-specific dialects within the MLIR framework.This allows the compiler to optimize tiled matrix multiplication by integrating accelerator buffer size,systolic array dimensions,double buffering strategies,and dataflow patterns.Furthermore,it implements efficient matrix transposition by adjusting data flow patterns according to the hardware architecture,eliminating the need for large-scale data exchange.The paper also implements convolution operator fusion and matrix multiplication-vector computation fusion based on systolic array features.Experimental results demonstrate an average speedup of 14.55× after transposition optimization,an average 41.59% speedup after operator fusion,and a comprehensive average speedup of 5.13% for BERT model execution.

Key words: Deep learning compiler, RISC-V, Accelerator, MLIR, Compilation optimization