Computer Science ›› 2021, Vol. 48 ›› Issue (6): 19-25.doi: 10.11896/jsjkx.200700198

• Computer Architecture • Previous Articles     Next Articles

List-based Software and Hardware Partitioning Algorithm for Dynamic Partial Reconfigurable System-on-Chip

GUO Biao1,2, TANG Qi2, WEN Zhi-min3, FU Juan4, WANG Ling1, WEI Ji-bo2   

  1. 1 College of Electrical and Information Engineering,Hunan University,Changsha 410082,China
    2 School of Electronic Science and Technology,National University of Defense Technology,Changsha 410073,China
    3 Vehicle Department of Changsha Rail Transit Operation Co.,Ltd,Changsha 410000,China
    4 Institute of System Engineering,Academy of Chinese PLA Military Science,Beijing 100101,China
  • Received:2020-07-30 Revised:2020-08-20 Online:2021-06-15 Published:2021-06-03
  • About author:GUO Biao,born in 1995,postgraduate.His main research interests include software defined radio and dynamic partially reconfiguration technology of FPGA.(
    TANG Qi,born in 1986,Ph.D,assistant professor.His main research interests include reconfigurable computing,embedded parallel computing,algorithm designand software defined system.

Abstract: Parallel computing is an important means to improve the utilization rate of system resources.More and more systems on multi-processor chip meet the requirements of different computing tasks by integrating processors with different functional characteristics.A heterogeneous multiprocessor system-on-chip (DPR-HMPSoC) with dynamic partial reconfigurability is widely used because of its good parallelism and high computing efficiency,while the software/hardware partitioning algorithm with low complexity and high solving performance is an important guarantee for giving full play to its computational performance advantages.The existing related software/hardware partitioning algorithms have high time complexity and insufficient support for the DPR-HMPSoC platform.In response to the above problems,this paper proposes a list heuristic software/hardware partitioning and scheduling algorithm.By constructing a scheduling list based on task priority,a series of operations such as task scheduling,mapping and FPGA dynamic partial reconfigurable area partitioning are completed.It introduces software application mode-ling,computing platform modeling,and the detailed design scheme of the proposed algorithm.The simulation experiment results show that the proposed algorithm can effectively reduce the solution time compared with the MILP and ACO algorithms,and the time advantage is proportional to the task scale.In terms of scheduling length,the average performance of the proposed algorithm is improved by about 10%.

Key words: Dynamic partial reconfigurable, FPGA, List-based heuristics, Scheduling, Software/hardware partitioning

CLC Number: 

  • TP302
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