Computer Science ›› 2021, Vol. 48 ›› Issue (4): 205-212.doi: 10.11896/jsjkx.200600089

• Computer Graphics & Multimedia • Previous Articles     Next Articles

FPGA-based CNN Image Recognition Acceleration and Optimization

QI Yan-rong1, ZHOU Xia-bing2, LI Bin1, ZHOU Qing-lei1   

  1. 1 School of Information Engineering,Zhengzhou University,Zhengzhou 450001,China
    2 School of Computer Science and Technology,Soochow University,Suzhou,Jiangsu 215006,China
  • Received:2020-06-24 Revised:2020-08-13 Online:2021-04-15 Published:2021-04-09
  • About author:QI Yan-rong,born in 1995,postgra-duate.Her main research interests include image processing and high-performance computing.(17319793885@163.com)
    LI Bin,born in 1986,Ph.D,associate professor.His main research interests include information security and high performance computing.
  • Supported by:
    National Key R&D Program “Public Safety Risk Prevention and Control and Emergency Technology Assembly” Key Special Project (2018XXXXXXX01) and National Natural Science Foundation of China(61702518).

Abstract: Currently,CNN has been widely used in many application scenarios,including image classification,speech recognition,video analysis,document analysis,etc.Because CNN is computationally intensive,it is often accelerated with GPUs.However,GPU has a high power consumption and is not suitable for CNN inference stage.Based on this,this paper studies the application method of FPGA-based CNN image recognition acceleration and optimization.The OpenCL SDK provided by Intel FPGA is used to design and optimize the CNN forward model on the FPGA board.First of all,for the calculation problem,through the division of functional modules,the advantages of FPGA’s high computing efficiency are fully utilized.Secondly,this paper optimizes the core algorithm to improve the running speed,analyzes the feature map processing operations,uses the parameter sharing strategy to reduce the amount of data storage,uses the pipeline to transfer data,and reduce the number of accesses to off-chip storage.Finally,it optimizes the design of data cache,data flow and loop to alleviate the on-chip resource constraints of FPGA,quantizes the parameters and reduce the amount of FPGA memory resources occupied.Experimental results show that FPGA has lower power consumption,CPU power consumption is 2.1 times that of FPGA,and GPU power consumption is 6.5 times that of FPGA.Compared with the methods proposed in the literature of related fields in recent years,the proposed method has higher throughput and computational performance.

Key words: CNN, Data flow optimization, FPGA, Image recognition, Module division, OpenCL

CLC Number: 

  • TP391
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