Computer Science

Computer Science ›› 2024, Vol. 51 ›› Issue (11A): 231100120-7.doi: 10.11896/jsjkx.231100120

• Computer Software & Architecture • Previous Articles     Next Articles

Reconfigurable Computing System for Parallel Implementation of SVM Training Based on FPGA

PENG Weidong1, GUO Wei1, WEI Lin2   

  1. 1 Institute of Electronic and Electrical Engineering,Civil Aviation Flight University of China,Guanghan,Sichuan 618300,China
    2 Institute of Flight Technology,Civil Aviation Flight University of China,Guanghan,Sichuan 618300,China
  • Online:2024-11-16 Published:2024-11-13
  • About author:PENG Weidong,born in 1968,professor.His main research interests include computer measurement and control and computer simulation.
    GUO Wei,born in 1998,postgraduate.His main research interests include embedded system and machine learning acceleration.
  • Supported by:
    Independent Research Project of Key Laboratory of Flight Techniques and Flight Safety(XYKY2023018) and Research and Innovation Team Project of Civil Aircraft Integrated Avionics Technology Research Institute(CZKY2023161).

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Abstract: To address the problems of high computational complexity and long training time faced by support vector machines when dealing with large-scale datasets,a reconfigurable computing system for parallel SVM training based on FPGA is designed.The hardware resource consumption and acceleration performance under different quantization methods are analyzed.By utilizing the stochastic gradient descent method for SVM training,the dimensions to be solved are associated with the sample dimensions,significantly reducing computational complexity compared to traditional quadratic programming-based methods.Additionally,a specialized parallel computing structure is designed using FPGA-based reconfigurable hardware platform to accelerate the SVM training process.The entire system is jointly simulated in software and hardware.Simulation results on four public datasets show that the overall model prediction accuracy exceeds 90%.During the training phase,compared to software implementation using the same algorithm,the proposed hardware implementation reduces the processing time for a single sample by at least two orders of magnitude under floating-point representation.Under fixed-point representation,the processing time for a single sample is reduced by up to three orders of magnitude.Compared to the hardware implementation based on quadratic programming problem solving,the processing speed for a single sample is improved by up to 394 times.

Key words: FPGA, Support vector machine, Reconfigurable system, Parallel computing, Stochastic gradient descent

CLC Number: 

  • TP181
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