Computer Science

Computer Science ›› 2024, Vol. 51 ›› Issue (6A): 230800138-9.doi: 10.11896/jsjkx.230800138

• Computer Software & Architecture • Previous Articles     Next Articles

FPGA Efficient Scalability Optimization of Dilithium

YAN Yunfei, LI Bin, WEI Yuanxin, ZHANG Bolin, MA Tianyi, ZHOU Qinglei   

  1. School of Computer and Artificial Intelligence,Zhengzhou University,Zhengzhou 450001,China
  • Published:2024-06-06
  • About author:YAN Yunfei,born in 1999,postgra-duate.His main research interests include post-quantum cryptography and high-performance computing.
    LI Bin,born in 1986,Ph.D,lecturer.His main research interests include high-performance computing and information security.
  • Supported by:
    Key Science and Technology Research Project of Henan Province,China(232102211055) and Research Project of Key Laboratory of Network Cryptography Technology of Henan Province,China(LNCT2022-A14).

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Abstract: To improve the operational efficiency of Dilithium in practical applications,an efficient field programmable gate array(FPGA) implementation of the Dilithium algorithm is proposed.Optimization is carried out in several aspects,including combining the Karatsuba-Offman algorithm(KOA) with the fast modular reduction algorithm to create a fast modular multiplication unit,optimizing the extensive polynomial multiplication achieved through number theoretic transform(NTT) implementation.Multiple RAM accesses are employed for polynomial coefficient operations,and a coefficient reading strategy tailored to the characteristics of the Dilithium algorithm is designed to achieve rapid and accurate reading of polynomial coefficients from RAM.For the sampling and hashing tasks in the scheme,the characteristics of the SHAKE algorithm series are analyzed,leading to the development of a low-latency and scalable Keccak hardware architecture,allowing it to execute different SHAKE algorithms based on the input signal.Experimental results demonstrate that the working frequency of the proposed algorithm is increased by 60.7%~131.9%,while balancing hardware resource consumption and execution efficiency.

Key words: Dilithium algorithm, FPGA, NTT, Hardware implementation

CLC Number: 

  • TP309.7
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