Computer Science

Computer Science ›› 2025, Vol. 52 ›› Issue (4): 94-100.doi: 10.11896/jsjkx.241000099

• Smart Embedded Systems • Previous Articles     Next Articles

Efficient Adaptive CNN Accelerator for Resource-limited Chips

PANG Mingyi1, WEI Xianglin2, ZHANG Yunxiang2, WANG Bin2, ZHUANG Jianjun1   

  1. 1 School of Electronics and Information Engineering,Nanjing University of Information Science & Technology,Nanjing 211800,China
    2 63rd Research Institute,National University of Defense Technology,Nanjing 210007,China
  • Received:2024-10-21 Revised:2025-02-22 Online:2025-04-15 Published:2025-04-14
  • About author:PANG Mingyi,born in 2001,postgra-duate.His main research interests include hardware acceleration and edge computing.
    WEI Xianglin,born in 1985,Ph.D,associate researcher.His main research interests include edge computing,deep learning and wireless network security.

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Abstract: This paper proposes an adaptive convolutional neural network accelerator(ACNNA) for non-GPU chips with limited resources,which can adaptively generate hardware accelerators based on resource constraints of hardware platform and convolutional neural network structures.Through its reconfigurable feature,ACNNA can effectively accelerate various layer combinations including convolutional layers,pooling layers,activation layers,and fully connected layers.Firstly,a resource folding multi-channel processing engine(PE) array is designed,which folds the idealized convolutional structure to save resources and unfolds on the output channel to support parallel computing.Secondly,multi-level storage and ping-pong caching mechanisms are adopted to optimize the pipeline,effectively improving data processing efficiency.Then,a resource reuse strategy under multi-level storage is proposed,which combined with the design space exploration algorithm can more reasonably schedule hardware resource allocation for network parameters,so that low resource chips can deploy deeper and more parameterized network models.Taking LeNet5 and VGG16 network models as examples,this paper validate ACNNA on the Ultra96 V2 development board.The results show that the ACNNA deployment of VGG16 consumes only 4% of resources of original network.At 100MHz main frequency,LeNet5 accelerator achieves a computing rate of 0.37 GFLOPS with a power consumption of 2.05W; VGG16 accelerator has a computing speed of 1.55 GFLOPS at a power consumption of 2.132W.Compared with existing work,ACNNA increases Frames Per Second(FPS) by over 83%.

Key words: Hardware acceleration, Convolutional neural network, Design space exploration strategy, Field programmable gate array

CLC Number: 

  • TP391
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